Altium

Design Rule Verification Report

Date: 17-11-2020
Time: 03:25:53
Elapsed Time: 00:00:02
Filename: C:\Users\subra\OneDrive\Desktop\altium\Recharge_Hub\Recharge_Hub_PCB.PcbDoc
Warnings: 0
Rule Violations: 20

Summary

Warnings Count
Total 0

Rule Violations Count
Clearance Constraint (Gap=10mil) (All),(All) 0
Short-Circuit Constraint (Allowed=No) (All),(All) 0
Un-Routed Net Constraint ( (All) ) 0
Modified Polygon (Allow modified: No), (Allow shelved: No) 0
Width Constraint (Min=10mil) (Max=100mil) (Preferred=40mil) (All) 0
Power Plane Connect Rule(Relief Connect )(Expansion=20mil) (Conductor Width=10mil) (Air Gap=10mil) (Entries=4) (All) 0
Hole Size Constraint (Min=1mil) (Max=100mil) (All) 12
Hole To Hole Clearance (Gap=10mil) (All),(All) 0
Minimum Solder Mask Sliver (Gap=10mil) (All),(All) 0
Silk To Solder Mask (Clearance=10mil) (IsPad),(All) 8
Silk to Silk (Clearance=10mil) (All),(All) 0
Net Antennae (Tolerance=0mil) (All) 0
Height Constraint (Min=0mil) (Max=1000mil) (Prefered=500mil) (All) 0
Total 20

Hole Size Constraint (Min=1mil) (Max=100mil) (All)
Hole Size Constraint: (135.827mil > 100mil) Pad BATT1-1(440.039mil,4910.669mil) on Multi-Layer Actual Hole Size = 135.827mil
Hole Size Constraint: (135.827mil > 100mil) Pad BATT1-2(1069.961mil,2737.441mil) on Multi-Layer Actual Hole Size = 135.827mil
Hole Size Constraint: (135.827mil > 100mil) Pad BATT2-1(1560.039mil,4910.669mil) on Multi-Layer Actual Hole Size = 135.827mil
Hole Size Constraint: (135.827mil > 100mil) Pad BATT2-2(2189.961mil,2737.441mil) on Multi-Layer Actual Hole Size = 135.827mil
Hole Size Constraint: (135.827mil > 100mil) Pad BATT3-1(2660.039mil,4900.669mil) on Multi-Layer Actual Hole Size = 135.827mil
Hole Size Constraint: (135.827mil > 100mil) Pad BATT3-2(3289.961mil,2727.441mil) on Multi-Layer Actual Hole Size = 135.827mil
Hole Size Constraint: (135.827mil > 100mil) Pad BATT4-1(3790.039mil,4897.244mil) on Multi-Layer Actual Hole Size = 135.827mil
Hole Size Constraint: (135.827mil > 100mil) Pad BATT4-2(4419.961mil,2724.016mil) on Multi-Layer Actual Hole Size = 135.827mil
Hole Size Constraint: (180mil > 100mil) Pad Free-(165mil,6115mil) on Multi-Layer Actual Hole Size = 180mil
Hole Size Constraint: (180mil > 100mil) Pad Free-(200mil,210mil) on Multi-Layer Actual Hole Size = 180mil
Hole Size Constraint: (180mil > 100mil) Pad Free-(4545mil,190mil) on Multi-Layer Actual Hole Size = 180mil
Hole Size Constraint: (180mil > 100mil) Pad Free-(4550mil,6130mil) on Multi-Layer Actual Hole Size = 180mil
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Silk To Solder Mask (Clearance=10mil) (IsPad),(All)
Silk To Solder Mask Clearance Constraint: (Collision < 10mil) Between Pad BATT1-1(440.039mil,4910.669mil) on Multi-Layer And Track (348.504mil,2296.693mil)(348.504mil,4913.425mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mil]
Silk To Solder Mask Clearance Constraint: (Collision < 10mil) Between Pad BATT1-2(1069.961mil,2737.441mil) on Multi-Layer And Track (1161.496mil,2296.693mil)(1161.496mil,2813.425mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mil]
Silk To Solder Mask Clearance Constraint: (Collision < 10mil) Between Pad BATT2-1(1560.039mil,4910.669mil) on Multi-Layer And Track (1468.504mil,2296.693mil)(1468.504mil,4913.425mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mil]
Silk To Solder Mask Clearance Constraint: (Collision < 10mil) Between Pad BATT2-2(2189.961mil,2737.441mil) on Multi-Layer And Track (2281.496mil,2296.693mil)(2281.496mil,2813.425mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mil]
Silk To Solder Mask Clearance Constraint: (Collision < 10mil) Between Pad BATT3-1(2660.039mil,4900.669mil) on Multi-Layer And Track (2568.504mil,2286.693mil)(2568.504mil,4903.425mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mil]
Silk To Solder Mask Clearance Constraint: (Collision < 10mil) Between Pad BATT3-2(3289.961mil,2727.441mil) on Multi-Layer And Track (3381.496mil,2286.693mil)(3381.496mil,2803.425mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mil]
Silk To Solder Mask Clearance Constraint: (Collision < 10mil) Between Pad BATT4-1(3790.039mil,4897.244mil) on Multi-Layer And Track (3698.504mil,2283.268mil)(3698.504mil,4900mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mil]
Silk To Solder Mask Clearance Constraint: (Collision < 10mil) Between Pad BATT4-2(4419.961mil,2724.016mil) on Multi-Layer And Track (4511.496mil,2283.268mil)(4511.496mil,2800mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mil]
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